Lãnh đạo Intel: Công nghệ chip đã bắt kịp TSMC, quy mô sản xuất thì cần thêm thời gian

The global semiconductor manufacturing landscape is undergoing a monumental paradigm shift, marked by fierce competition, multi-billion-dollar investments, and relentless technological innovation. In recent statements shared on the Dwarkesh podcast, top executives at Intel Corporation outlined their ambitious roadmap to close the gap with industry titan Taiwan Semiconductor Manufacturing Company (TSMC). While Intel’s leadership expressed profound confidence in achieving technological parity—and in some areas, superiority—they candidly acknowledged that matching TSMC’s colossal production scale will require a considerable investment of time and steady execution.

This comprehensive look into Intel’s foundry strategy highlights critical advancements in lithography, backside power delivery, and advanced transistor architectures. As the semiconductor industry pushes past the nanometer threshold into uncharted physical territory, the race to build the world’s most advanced microchips is no longer solely about raw transistor density; it is heavily defined by manufacturing yield, supply chain reliability, and the successful commercialization of revolutionary tooling.

Bridging the Technological Divide: The Power of High-NA EUV and PowerVia

For years, TSMC has maintained an undisputed lead in contract chip manufacturing, supplying cutting-edge silicon to tech giants such as Apple, NVIDIA, and AMD. However, Intel’s executive team believes that the performance gap—often measured in single-digit percentage variations—is no longer an insurmountable obstacle for the American semiconductor pioneer.

Chris Auth, Vice President and General Manager of Technology Manufacturing Development and Foundry Customer Engagement at Intel, provided deep technical insights into how the company is leveraging High-Numerical Aperture Extreme Ultraviolet (High-NA EUV) lithography to leapfrog traditional manufacturing bottlenecks.

Traditionally, as feature sizes on silicon wafers shrink, wiring congestion on the front side of the wafer becomes a severe limitation. Signal wires and power delivery lines must compete for microscopic space on the same plane, forcing manufacturers to draw extremely thin metal layers packed tightly together. When wiring gets too dense for standard lithography tools to pattern in a single exposure, foundries must resort to complex multi-patterning techniques. Multi-patterning involves splitting a single circuit layout across multiple exposures and subsequently aligning them, a process that significantly increases manufacturing costs, extends production cycles, and introduces alignment errors that degrade overall chip yields.

Intel aims to bypass these limitations through two core innovations: High-NA EUV lithography and its proprietary backside power delivery technology, known as PowerVia. By shifting the power delivery network to the backside of the silicon wafer, Intel frees up the front side exclusively for signal routing. This architectural reorganization drastically reduces wiring congestion on the front surface.

Combined with the superior resolution of High-NA EUV machinery—which gathers light from a wider angle to project finer circuit details in a single pass—Intel can print complex circuitry directly without relying heavily on multi-patterning. While High-NA EUV tools are exceptionally expensive and feature a smaller exposure field requiring the stitching of larger chips, Intel’s leadership argues that mastering this technology provides a decisive advantage in transistor scaling and efficiency.

Navigating the 14A Roadmap and Customer Engagement

Building upon these foundational innovations, Intel has positioned its upcoming 14A (1.4-nanometer class) process node as a cornerstone for future foundry growth. According to Chris Auth, the 14A process is already available as a tangible option within the company’s internal design rule decks, and Intel is actively engaged in direct technical discussions with prospective external foundry customers.

However, moving advanced nodes from paper to high-volume production requires winning the trust of fabless chip designers who have relied on TSMC for decades. Pushkar Ranade, Director of Technology Foundry at Intel, acknowledged the vast disparity in wafer manufacturing scale between Intel and TSMC. Because TSMC commands the lion’s share of global advanced foundry capacity, Intel’s journey to matching this operational scale will inherently be gradual and measured.

Despite the differences in production volume, Ranade firmly asserted that Intel has achieved technological milestones that rival or exceed those of its chief competitor. He emphasized that while performance metrics can fluctuate by a few percentage points, the ultimate arbiter of success is execution. Semiconductor fabrication plants must achieve high product recovery yields rapidly and reliably to fulfill massive, high-volume supply orders on strict schedules. For major enterprise customers, operational consistency and proven yield stability take precedence over marginal improvements in raw performance or area scaling. Consequently, major external clients are expected to transition significant wafer allocations to Intel only after the company conclusively demonstrates high, repeatable yields at scale.

Beyond FinFET: Gate-All-Around and Stacked Semiconductors

As the semiconductor industry looks beyond current architectures, research and development teams are already exploring the next generation of transistor designs. Jack Kavalieros, Vice President of Component Research at Intel, discussed the complexities of vertical stacking for complementary field-effect transistors (CFETs), involving the integration of both p-type and n-type semiconductor devices.

Connecting semiconductor blocks vertically along the Z-axis introduces unprecedented manufacturing challenges, particularly concerning frame yields during the creation and filling of microscopic trenches. Without flawless process control, vertical stacking can inadvertently trap air pockets or create voids, which compromise the structural and electrical integrity of the final chip. Solving these nanoscale manufacturing hurdles is essential for sustaining Moore’s Law as traditional two-dimensional scaling approaches fundamental physical limits.

The Broader Market Implications and Competitive Outlook

The competition between Intel, TSMC, and other major players like Samsung Electronics underscores the ultra-high stakes of the modern semiconductor supply chain. While Samsung has heavily invested in gate-all-around (GAA) transistor technology, it has historically faced persistent challenges regarding thermal management, power efficiency, and yield stabilization on its most advanced nodes. These struggles highlight the immense difficulty of scaling semiconductor manufacturing, proving that capital expenditure alone cannot guarantee commercial success.

For Intel, the transformation into a premier independent foundry is a multi-year marathon rather than a sprint. The company’s strategic bet on High-NA EUV and backside power delivery represents a calculated risk aimed at leapfrogging incremental process generations. If Intel can successfully scale its manufacturing volume, stabilize its production yields, and deliver on its 14A roadmap, it stands to fundamentally reshape the geopolitical and economic landscape of global microchip production.

As the industry moves toward 2025 and beyond, the success of Intel Foundry will be judged not by theoretical technological superiority on a whiteboard, but by the volume of commercial silicon successfully delivered to the world’s most demanding technology companies.